Start with the architecture.
Synthesize the NTF, select a topology, and scale states to your integrator swing limits. Inspect the ABCD matrix and a, g, b, c coefficients.
MATLAB DESKTOP APP / VERSION 1.0
From ADC specs.
To circuit-ready
parameters.
Design and verify incremental sigma-delta ADCs in one traceable workflow. Move from NTF synthesis to capacitor ratios, nonideal behavior and statistical signoff.
MATLAB R2022b+ Local, offline operation Ten-stage verification English & Chinese manuals
Screenshot: completed behavioral-model workflow with the ideal continuous-mode FFT selected. Displayed metrics are results for the shown settings, not guaranteed hardware specifications.
01 / CAPABILITIES
The decisions between
an NTF and a circuit.
See how implementation choices affect your design, with coefficients, waveforms and validation gates at every stage.
Get implementable ratios.
Convert coefficients to common-denominator integer capacitor ratios. See unit counts, coefficient error, thermal-noise sizing and differential capacitance.
Put amplifiers in the loop.
Configure each integrator’s gain, bandwidth, slew rate and output swing. Use manual gain or automatic search and inspect the resulting evidence.
See beyond the ideal model.
Explore input-referred sampling thermal noise, dither and capacitor mismatch. Compare static error, dynamic FFT and Monte Carlo yield.
Co-design the conversion.
Evaluate incremental reset and finite-window sinc decoding. Scan M candidates against your deterministic-error budget.
Keep the evidence.
Follow per-stage validation gates, apply two-point calibration, save projects and export a reproducible design package after final acceptance.
02 / WORKFLOW
Every step has evidence.
Run a selected stage while exploring. Run through final signoff when you are ready to evaluate the complete design.
- 01
Specification
Ranges, targets and budgets
- 02
Topology
NTF, ABCD and state scaling
- 03
Continuous FFT
SNDR and dynamic ENOB
- 04
Incremental conversion
Reset, sinc decoder and M
- 05
Capacitor mapping
Integer ratios and capacitance
- 06
Amplifier behavior
Finite gain and settling
- 07
Noise and dither
FFT and statistical DC sweep
- 08
Mismatch Monte Carlo
Static, dynamic and combined yield
- 09
Calibration
Per-device gain and offset
- 10
Final signoff
Combined budget and coverage
A completed simulation and a passing design are distinct. Validation gates show the actual value, limit and reason when a design fails.
03 / DESIGN EVIDENCE
Take the parameters
into your circuit model.
Inspect the synthesized coefficients in the App, then use the design parameters to build and verify your own switched-capacitor implementation.
Inspect the design
NTF, ABCD and coefficients stay visible throughout the workflow.
Build the implementation
A second-order CIFF circuit-model example created from App parameters.
04 / NONIDEAL VERIFICATION
See what limits
the result.
Move beyond the ideal baseline with sampling thermal noise, DAC mismatch, DEM and static-error evidence. Enlarge any capture to inspect the settings and reported metrics.
Thermal-noise impact
Inspect the dynamic FFT after sampling thermal noise is introduced.
Mismatch with DWA
Review a trial-level dynamic spectrum instead of relying only on aggregate yield.
Static conversion error
Keep static ENOB_pp separate from FFT-derived dynamic ENOB.
These results belong to the App’s behavioral workflow. For Cadence circuit-model FFT results, see the separate CIFF model
CIRCUIT-MODEL VALIDATION EXAMPLES
Check the design
in a circuit model.
Cadence circuit-model examples using App design parameters. Compare the ideal baseline, sampling thermal noise, DAC mismatch and mismatch with DWA.
Ideal-model baseline
Ideal circuit-model FFT: a baseline for comparing the non-ideal cases below.
Input sampling thermal noise
With input sampling thermal noise enabled, the displayed ENOB remains above 18 bits.
DAC capacitor mismatch
DAC mismatch without DWA. The displayed setup uses a 35.6 fF unit capacitor and 0.45% mismatch sigma.
DAC mismatch with DWA
The DAC mismatch case with data-weighted averaging enabled. Compare the in-band spectrum with the mismatch-only capture.
These are separate circuit-model checks, not a combined thermal-noise-plus-mismatch run. The Cadence model files are not included in the App purchase. View the separate CIFF Cadence model
05 / GET THE APP
Your design.
Your local workspace.
A downloadable MATLAB App for engineers and researchers working on incremental sigma-delta ADCs.
Before you buy
Requires MATLAB R2022b or newer and a separately installed, compatible Delta-Sigma Toolbox. Parallel acceleration requires Parallel Computing Toolbox.
Read installation requirementsRELEASE APPv1.0
Sigma-Delta ADC Designer
$99.00USD · one-time purchase
- Complete ten-stage App workflow
- MATLAB .mltbx installer
- English interface
- English and Chinese user manuals
- Download after payment + email copy
- Local offline use
- Personal or internal business use
Download after payment, with an email copy.
Your private download will appear on the confirmation page once payment is verified. We will also email the same link. Please double-check your checkout email address.
Final price and applicable taxes are shown at checkout.
Read the license terms06 / QUESTIONS
A few details
before you start.
CONTACT