Integrator non-idealities
Finite DC gain A0, gain-bandwidth (GBW) and slew rate model the departure from ideal integration and settling.
CADENCE SIMULATION MODEL
Second-order CIFF.
A Cadence model.
A second-order, 4-bit sigma-delta modulator in Cadence. Study a 250 Hz signal band at a 256 kHz sampling rate, then see what finite amplifier gain, settling, sampling noise and DAC mismatch do to the spectrum.
This is a separate model-file product—not the MATLAB App and not a transistor-level silicon IP release.
DESIGN OPERATING POINT
Second order. Four bits. OSR 512.
The supplied design uses VDD = 1.8 V, VREF = 1.2 V and VCM = 0.9 V. Its input range is ±0.75 VREF, or ±0.9 V. The nominal signal bandwidth is fs / (2 × OSR) = 250 Hz.
- Architecture
- Second-order CIFF
- Quantizer
- 4-bit
- Oversampling ratio
- 512
- Sampling frequency
- 256 kHz
- Signal bandwidth
- 250 Hz
- Supply · VDD
- 1.8 V
- Reference · VREF
- 1.2 V
- Common mode · VCM
- 0.9 V
- Input range
- ±0.75 VREF (±0.9 V)
CIRCUIT & NON-IDEALITIES
More than an ideal integrator loop.
The model brings the CIFF signal paths into a Cadence circuit-simulation testbench, with two integrators, a multi-bit quantizer and DAC feedback. Use it to examine implementation effects before moving to a transistor-level design.
The CIFF modulator testbench
Two integrator stages, feedforward summation and multi-bit DAC feedback. Click to enlarge the original capture.
Sampling & switching
Input sampling thermal noise and switch non-idealities are included, so the model is not limited to an ideal discrete-time signal loop.
DAC mismatch & DWA
DAC capacitor mismatch and data-weighted averaging are modeled. Compare the spectra with and without DWA rather than judging mismatch from the ideal FFT alone.
CADENCE SIMULATION RESULTS
See the effect, not just the final number.
The reported model design achieves ENOB above 18 bits. These four existing Cadence captures show the ideal baseline and individual noise/mismatch checks; the sampling-noise case reports 18.85 bits. They are the same circuit-model results shown on the App page, not MATLAB App FFT outputs.
Ideal-model baseline
20.19 bits ENOB
Ideal circuit-model FFT: a baseline for comparing the non-ideal cases below.
Input sampling thermal noise
18.85 bits ENOB
With input sampling thermal noise enabled, the displayed ENOB remains above 18 bits.
DAC capacitor mismatch
18.05 bits ENOB
DAC mismatch without DWA. The displayed setup uses a 35.6 fF unit capacitor and 0.45% mismatch sigma.
DAC mismatch with DWA
20.57 bits ENOB
The DAC mismatch case with data-weighted averaging enabled. Compare the in-band spectrum with the mismatch-only capture.
FFT captures: 8192 samples, 256 kHz sampling rate, Hanning window and a displayed analysis band of 31.25–250 Hz. These are separate simulation conditions, not evidence that all non-idealities are enabled simultaneously. In particular, the 20.57-bit DWA result is not a combined thermal-noise-plus-mismatch result. ENOB depends on the input, enabled effects and FFT settings; these are model simulations, not measured silicon.
ABOUT THIS PRODUCT
From architecture to circuit-model simulation.
The CIFF architecture uses feedforward paths from the integrator states to the quantizer input. This listing is for a second-order sigma-delta modulator model in Cadence, rather than a complete incremental ADC with a reset controller and digital decimation filter.
A separate Cadence model
The model-file release is independent of Sigma-Delta ADC Designer. Buying the MATLAB App does not include this model, and this model does not include the App.
Simulation, not silicon signoff
A circuit model is a starting point for design and verification. It is not a guarantee of transistor-level, post-layout or measured silicon performance.
Ready to simulate
The ZIP includes the simulation model files. Import the supplied library into Cadence and run the included testbench directly. A compatible Virtuoso/Spectre installation is required; Cadence software and EDA licenses are not included.
PACKAGE & SETUP
Extract, import and simulate.
The ZIP contains the CIFF model library, schematic and symbol views, simulation model files, ADE/Maestro simulation setup and Verilog-A support cells. The model files needed for simulation are already included; import the package to run the supplied testbench directly. This is the second-order, 4-bit model package; it does not include the MATLAB App, a reset controller or a digital decimation filter.
- Extract the ZIP into a writable simulation workspace; preserve its directory structure.
- Import the supplied model library into Cadence.
- Open the included testbench and its ADE/Maestro simulation setup.
- Run the supplied transient simulation and review the FFT results. Use the input, clock, reference and noise settings to explore the different modeled cases.
Simulation results depend on your model settings and environment; no measured-silicon or ENOB guarantee is offered. The purchaser license and redistribution restrictions in our terms apply to this model.
Interested in using the model? Contact sigmadeltastudio@163.com to discuss your simulation environment.