# Sigma-Delta ADC Designer Help

## Purpose

Sigma-Delta ADC Designer guides a design through a traceable ten-stage workflow. It supports CIFF, CIFB, CRFF, CRFB, and custom ABCD models; integer quantizer level counts from 2 to 256; streaming and incremental-reset conversion; sinc1 through sinc6 decoders; capacitor mapping; DEM; finite op-amp performance; thermal noise; dither; mismatch Monte Carlo analysis; calibration; and final statistical signoff.

The App distinguishes a completed simulation from a passing design. A stage can report `pass`, `fail`, `incomplete`, or `inconclusive`. Only a `pass` result at Stage 10 enables export of a reproducible design package.

The optional `SDADC_DELSIG_ROOT` environment variable may point to an external Delta-Sigma Toolbox installation when it is not already on the MATLAB path.

## Quick Start

1. Select the architecture, modulator order, quantizer level count, conversion mode, sinc order, and M/OSR in the left panel.
2. Set VREF, VDD, input range, ENOB targets, sampling rate, signal bandwidth, FFT stimulus, and validation coverage.
3. Configure every integrator's swing limit, A0 mode, A0, GBW, SR, and large-/small-signal settling allocation.
4. Configure the unit capacitor, differential total-capacitance limit, coefficient error limit, DAC DEM mode, mismatch sigma, yield target, noise, and dither.
5. Use **Debug Preview** while adjusting a design. Use **Final Signoff** for acceptance evidence.
6. Select a stage and click **Run Selected Stage**, or click **Run Through Final Signoff**.
7. Inspect the tables, coefficients, ABCD matrix, FFT spectrum, static error, integrator states, ENOB distribution, and failed-gate diagnostics.
8. Export only after all required final gates pass.

Final coverage is never silently reduced. Preview has independent FFT, discard, DC-sweep, and Monte Carlo settings and cannot produce a Final PASS.

## The Ten Stages

### 1. Specification and Normalization

Defines VREF, VDD, sample rate, signal bandwidth, input range, target ENOB, deterministic-error budget, and per-integrator voltage limits. Static LSB size is referenced to the maximum input span accepted by state scaling, not to the FFT stimulus amplitude.

### 2. Topology, NTF, ABCD, and Scaling

Calls `synthesizeNTF`, `realizeNTF`, `stuffABCD`, and `scaleABCD` when applicable. The App displays the NTF expression, numerator, denominator, poles, zeros, scaled ABCD matrix, a/g/b/c coefficients, scaling matrix, maximum stable input `vinmax`, and state peaks. The physical state limits passed to `scaleABCD` are derived from each integrator's configured voltage limit.

### 3. Continuous-Mode FFT

Runs the nonlinear modulator for `discard + NFFT` samples and applies a periodic Hann window. Dynamic FFT evidence classifies the DC bin and the adjacent Hann DC-main-lobe bin as DC evidence, excludes both from SNDR, and masks them in the dynamic-metric plot. It does not subtract the ordinary sample mean, because that operation can alter the first positive-frequency bin of a finite correlated DAC sequence. SNDR integrates the remaining in-band noise and distortion while excluding the fundamental and harmonic main-lobe bins. The FFT plot reports SNDR and ENOB. Runtime is usually dominated by sample-by-sample modulator simulation, not by the FFT function itself.

### 4. Incremental Reset, sinc Decoder, and M

Evaluates the configured M candidates with the finite-window sinc decoder. It reports calibrated endpoint-fit INL, maximum static error, and peak-to-peak static ENOB. The smallest candidate meeting the deterministic-error budget is selected; no monotonic-performance assumption is made.

### 5. Integer Capacitor Mapping

Maps nonzero a/g/b/c coefficients to common-denominator integer capacitor ratios. The first-stage shared sampling/DAC-feedback array is sized from the fully differential `4kT/C` thermal-noise requirement before coefficient quantization. The total-capacitance gate uses the sum of both differential sides. Coefficients with `abs(g) < 0.01` are implemented as zero.

The unary DAC uses two-state elements connected to positive or negative reference. Available selection modes are Static Mapping, DWA, ILA Rotation, ILA Addition, and Butterfly. Butterfly requires a power-of-two unary element count; for example, 17 quantizer levels provide 16 unary elements.

### 6. Finite A0, GBW, and SR

Each integrator can use manual A0 or automatic A0 search. Automatic search starts at the configured lower bound and selects the lowest value that satisfies system-level static INL, FFT, reset, and swing gates. The accepted finite-A0 FFT and DC sweep are published in the Stage 6 FFT and Static Error tabs. GBW and SR are checked with the configured large-/small-signal settling allocation. Manual A0 is simulated directly and is never overwritten by the automatic result.

### 7. Thermal Noise and Dither

The first-stage sampling thermal noise is injected at the ADC input. Its fully differential variance is `4kT/Csample`. The shared first-stage sampling/DAC-feedback capacitor is counted once; integration capacitance and later-stage capacitances do not add independent thermal-noise terms under the current model assumptions.

Stage 7 runs a finite-A0 continuous FFT with the configured thermal noise and dither. It also runs a repeated statistical DC sweep. Every sample, DC point, and repeat receives an independent Gaussian thermal-noise value derived from a fixed master seed, so results are random in the model but exactly reproducible. `Stage-7 Noise DC Repeats` controls how many independent conversions are averaged at each input point. The App reports the mean calibrated static transfer, per-point sigma, FFT/DC/total runtime, execution strategy, and worker count.

Independent repeated DC sweeps can run on separate parallel workers. Samples inside one modulator record remain sequential because each state depends on the preceding sample. Preview and Final profiles continue to control the visible FFT and DC point counts.

Dither is injected before the quantizer. Supported sequences are PRBS, independent binary Bernoulli, uniform, and TPDF. Enabling dither activates the separately configured per-integrator dither swing limits. A Stage 7 PASS verifies the analytical budget, the configured dynamic FFT, the repeated mean DC transfer, and state limits; it does not by itself prove that every possible idle tone is removed.

The general noise-source interface reserves white-noise, 1/f-noise, combined, and imported-PSD descriptions. The present final sampling-noise contract uses the explicitly documented first-stage thermal-noise model.

### 8. Mismatch Monte Carlo

Creates independent unit-capacitor mismatch instances and reruns static and continuous-FFT evidence for every trial using the selected DEM mode. Static yield, FFT yield, and combined yield must each meet the configured target. The App displays the worst-trial FFT and the ENOB distribution.

### 9. Digital Calibration

Applies per-device two-point gain/offset calibration when enabled, then recomputes full-range static INL using the physical coefficients, DAC mismatch, DEM sequence, and finite op-amp behavior inherited from earlier stages. Two-point calibration removes offset and gain but not local periodic INL or higher-order nonlinearity.

### 10. Final Statistical Signoff

Requires Stages 1 through 9 to pass and checks the final contract

`deterministic peak-to-peak error + sigma multiplier * output-noise sigma <= 1 LSB`.

It also checks output rounding, state peaks, final FFT/DC/Monte Carlo coverage, and mismatch yield. Missing required evidence produces `incomplete` or `inconclusive`, never a false PASS.

## Important Configuration Notes

- `Quantizer Levels` is the actual level count, not a bit count. A conventional 4-bit quantizer uses 16 levels and 15 unary DAC elements.
- `FFT Input Amplitude / VREF` controls only the sine stimulus. It does not redefine the static LSB.
- `FFT Input Frequency` is mapped to the nearest coherent in-band bin for the active NFFT.
- Normal and dither swing limits are independent and are specified per integrator as fractions of VDD.
- `Differential Total Capacitance Limit` includes both physical differential sides.
- `Sampling Thermal Noise Sigma (V)` is the standard deviation of the first-stage input-referred sampled thermal noise.
- Preview results are for debugging. Restore Final Signoff before accepting or exporting a design.

## Performance and Cancellation

Independent DC points and Monte Carlo trials can use `parfor`. Select an appropriate worker limit for available memory; more workers can increase memory pressure. Background work can be cancelled immediately when it runs in a cancellable future. A foreground parallel stage uses cooperative cancellation and stops at the next safe stage boundary so partial evidence is never accepted as complete.

## Project Files

**Save Project** stores the current editable design configuration in an
`.sdadcproj` file. **Open Project** validates that file, restores every design
input and per-integrator setting, and clears evidence from the previously open
design. The restored workflow therefore starts in the pending state and must
be rerun before export. A project cannot be opened while a workflow is active.

## Reproducible Export

A passing final export contains the project snapshot, model and coefficients, capacitor table, op-amp requirements, digital filter information, stage evidence, random keys, source hash, validation scripts, and report artifacts. Reproduction on another computer requires a compatible MATLAB release and the required licensed toolboxes, including the Delta-Sigma Toolbox functions used by the selected topology flow.

## Troubleshooting

- If a stage fails, open **Validation Gates** and read `Actual`, `Limit`, and `Unit`.
- If the waveform does not change when selecting a stage, rerun that stage after editing inputs and confirm that its status is not `stale`.
- If MATLAB memory use is excessive, reduce preview coverage or worker count, close unused figures, and reserve full coverage for Final Signoff.
- If `synthesizeNTF` or `scaleABCD` is missing, install and add the compatible Delta-Sigma Toolbox to the MATLAB path.
- If Stage 10 fails while earlier stages pass individually, inspect the combined 1-LSB budget and final coverage gates; individually acceptable error terms can still exceed the combined limit.
- The default 18-bit continuous-FFT target corresponds to `6.02 * 18 + 1.76 = 110.12 dB` required SNDR.